Low-Power Vertical Tunnel Field-Effect Transistor Ternary Inverter

In this study, vertical tunnel FET-based ternary CMOS (T-CMOS) is introduced and its electrical characteristics are investigated using TCAD device mixed-mode simulations with experimentally calibrated tunneling parameters. This new T-CMOS utilizes two different types of currents to form three output voltage states: (1) source-to-drain current; (2) conventional source-to-channel current. To a half supply (V DD ) during the inverter operation, n-/p-type devices proposed designed have constant current regardless gate xmlns:xlink="http://www.w3.org/1999/xlink">GS by nitride spacer between drain. Also, typical binary operation performed tunneling. transfer (VTC), it confirmed that there clear V state after matching devices. It revealed stable cannot be achievable if mismatched workfunction, dielectric thickness, interface trap variations, implying crucial obtain operations.